This invention relates to implementing mixed-precision floating-point operations in programmable integrated circuit devices such as, e.g., programmable logic devices (PLDs).
As applications for which PLDs are used increase in complexity, it has become more common to design PLDs to include specialized processing blocks in addition to blocks of generic programmable logic resources. Such specialized processing blocks may include a concentration of circuitry on a PLD that has been partly or fully hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. A specialized processing block may also contain one or more specialized structures, such as an array of configurable memory elements. Examples of structures that are commonly implemented in such specialized processing blocks include: multipliers, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/SIPO/RAM/ROM/CAM blocks and register files), AND/NAND/OR/NOR arrays, etc., or combinations thereof.
One particularly useful type of specialized processing block that has been provided on PLDs is a digital signal processing (DSP) block, which may be used to process, e.g., audio signals. Such blocks are frequently also referred to as multiply-accumulate (“MAC”) blocks, because they include structures to perform multiplication operations, and sums and/or accumulations of multiplication operations.
For example, PLDs sold by Altera Corporation, of San Jose, Calif., as part of the STRATIX® family, include DSP blocks, each of which may include four 18-by-18 multipliers. Each of those DSP blocks also may include adders and registers, as well as programmable connectors (e.g., multiplexers) that allow the various components to be configured in different ways. In each such block, the multipliers can be configured not only as four individual 18-bit-by-18-bit multipliers, but also as four smaller multipliers, or as one larger (36-bit-by-36-bit) multiplier. In addition, one 18-bit-by-18-bit complex multiplication (which decomposes into two 18-bit-by-18-bit multiplication operations for each of the real and imaginary parts) can be performed.
Multiplication operations may require different levels of precision. Double-precision operations typically involve numbers having twice as many digits in their mantissas as the numbers involved in single-precision operations. Therefore, particularly in the case of floating-point operations, double-precision multiplication operations typically involve large multiplications—e.g., 54-bit-by-54-bit multiplications—as compared to single-precision multiplication operations which typically involve at most 36-bit-by-36-bit multiplications.
Larger multiplications can be performed by using more of the 18-bit-by-18-bit multipliers—e.g., from other DSP blocks. For example, a 54-bit-by-54-bit multiplier can be decomposed, by linear decomposition, into a 36-bit-by-36-bit multiplier (which uses the four 18-bit-by-18-bit multipliers of one DSP block), two 36-bit-by-18-bit multipliers (each of which uses two 18-bit-by-18-bit multipliers, for a total of four additional 18-bit-by-18-bit multipliers, consuming another DSP block), and one 18-bit-by-18-bit multiplier, consuming a portion of a third DSP block. Thus, using 18-bit-by-18-bit multipliers, nine multipliers are required to perform a 54-bit-by-54-bit multiplication.
The number of multipliers needed typically is inflated in mixed-precision operations, because the lower precision operand is typically “promoted”—i.e., converted—to the higher precision before the operation, so that the higher precision of the higher-precision operand can be maintained. Thus, when multiplying a double-precision number by a single-precision number, the single-precision number is converted to a double-precision number and the operation is performed as a double-precision operation—e.g., as a 54-bit-by-54-bit multiplication.
The same holds true—for the same reasons—when carrying out mixed-precision division operations using multiplication-based techniques.